.jpg)
OEM DDR RAM MEMORY
8.9 USD
| Min. Order: | 500 piece |
|---|---|
| Payment Terms: | T/T or Western Union |
| Supply Ability: | 1000000000000 |
| Place of Origin: | Guangdong |
Company Profile
| Location: | Shenzhen, Guangdong, China (Mainland) |
|---|---|
| Business Type: | Manufacturer |
Product Detail
| Means of Transport: | EMS, DHL or UPS etc. |
|---|---|
| Brand Name: | Kingston |
| Function: | Store the datas |
| Certificate: | CE,Rohs |
| Export Area: | worldwide |
| Cooperative Company: | Shenzhen Mainbert Technology |
| Production Capacity: | 1000000000000 |
| Packing: | retail sealed packing |
| Delivery Date: | 3-5 working dyas |
Product Description
OEM DDR RAM MEMORY
1) DDR 400/333 & DDRII 533/667/800MHz
2) 168/184/240-pin socket type dual in line memory module (DIMM)
3) 2.6V power supply
4) Data rate: 400/333/533/667/800Mbps (max. )
5) 2.5 V (SSTL-2 compatible) I/O for DDR I products, 1.8V power supply for DDR II
products
6) Double data rate architecture, two data transfers per clock
7) Bi-directional, data strobe (DQS) is transmitted/received with data, to be
Used in capturing data at the receiver
8) Data inputs and outputs are synchronized with DQS
9) DQS is edge aligned with data for read, center aligned with data for write
10) Differential clock inputs (CK and CK)
11) DLL aligns DQ and DQS transitions with CK transitions
12) Commands entered on each positive CK edge, data referenced to both
Edges of DQS
13) Auto pre-charge option for each burst access
14) Programmable burst length: 2, 4, 8
15) Programmable/CAS latency (CL): 3
16) Programmable output driver strength: Normal/weak
17) Refresh cycles: (8192 refresh cycles/64ms)
18) 7.8US maximum average periodic refresh interval
19) 2 variations of refresh
20) Auto refresh
21) Self refresh1) DDR 400/333 & DDRII 533/667/800MHz
2) 168/184/240-pin socket type dual in line memory module (DIMM)
3) 2.6V power supply
4) Data rate: 400/333/533/667/800Mbps (max. )
5) 2.5 V (SSTL-2 compatible) I/O for DDR I products, 1.8V power supply for DDR II
products
6) Double data rate architecture, two data transfers per clock
7) Bi-directional, data strobe (DQS) is transmitted/received with data, to be
Used in capturing data at the receiver
8) Data inputs and outputs are synchronized with DQS
9) DQS is edge aligned with data for read, center aligned with data for write
10) Differential clock inputs (CK and CK)
11) DLL aligns DQ and DQS transitions with CK transitions
12) Commands entered on each positive CK edge, data referenced to both
Edges of DQS
13) Auto pre-charge option for each burst access
14) Programmable burst length: 2, 4, 8
15) Programmable/CAS latency (CL): 3
16) Programmable output driver strength: Normal/weak
17) Refresh cycles: (8192 refresh cycles/64ms)
18) 7.8US maximum average periodic refresh interval
19) 2 variations of refresh
20) Auto refresh
21) Self refresh
1) DDR 400/333 & DDRII 533/667/800MHz
2) 168/184/240-pin socket type dual in line memory module (DIMM)
3) 2.6V power supply
4) Data rate: 400/333/533/667/800Mbps (max. )
5) 2.5 V (SSTL-2 compatible) I/O for DDR I products, 1.8V power supply for DDR II
products
6) Double data rate architecture, two data transfers per clock
7) Bi-directional, data strobe (DQS) is transmitted/received with data, to be
Used in capturing data at the receiver
8) Data inputs and outputs are synchronized with DQS
9) DQS is edge aligned with data for read, center aligned with data for write
10) Differential clock inputs (CK and CK)
11) DLL aligns DQ and DQS transitions with CK transitions
12) Commands entered on each positive CK edge, data referenced to both
Edges of DQS
13) Auto pre-charge option for each burst access
14) Programmable burst length: 2, 4, 8
15) Programmable/CAS latency (CL): 3
16) Programmable output driver strength: Normal/weak
17) Refresh cycles: (8192 refresh cycles/64ms)
18) 7.8US maximum average periodic refresh interval
19) 2 variations of refresh
20) Auto refresh
21) Self refresh1) DDR 400/333 & DDRII 533/667/800MHz
2) 168/184/240-pin socket type dual in line memory module (DIMM)
3) 2.6V power supply
4) Data rate: 400/333/533/667/800Mbps (max. )
5) 2.5 V (SSTL-2 compatible) I/O for DDR I products, 1.8V power supply for DDR II
products
6) Double data rate architecture, two data transfers per clock
7) Bi-directional, data strobe (DQS) is transmitted/received with data, to be
Used in capturing data at the receiver
8) Data inputs and outputs are synchronized with DQS
9) DQS is edge aligned with data for read, center aligned with data for write
10) Differential clock inputs (CK and CK)
11) DLL aligns DQ and DQS transitions with CK transitions
12) Commands entered on each positive CK edge, data referenced to both
Edges of DQS
13) Auto pre-charge option for each burst access
14) Programmable burst length: 2, 4, 8
15) Programmable/CAS latency (CL): 3
16) Programmable output driver strength: Normal/weak
17) Refresh cycles: (8192 refresh cycles/64ms)
18) 7.8US maximum average periodic refresh interval
19) 2 variations of refresh
20) Auto refresh
21) Self refresh
